Sr. Digital Verification Engineer (CIS)
About The Position
Samsung R&D Center is looking for Sr. Digital Verification Engineer to join our team.
Samsung (SIRC), shaping the world of tomorrow, Today. Focusing beyond the horizon and pushing exciting developments in many key areas of technology. Samsung is creating a new era of continuous innovation, bringing value and contribution to society and creating a workplace where our employees can enjoy making the most of their talent, creativity and passion.
The Verification Cmos-Image-Sensor-Team is required to tackle the full flow of verification, from block & IP level to system level, including interfaces & deep understanding of all design flow and technical teams (such as Digital & FW).
We are looking for people with a broad set of technical skills, who are ready to tackle some of technology’s greatest challenges, who have the ability to think out of the box and bring the disruptive technologies that will define our future.
What will you do?
· Responsible for the full life cycle of verification, from verification planning to test execution, to collecting and closing coverage.
· Plan the verification of complex digital design from block level up to system level, by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
· Create a constrained-random verification environment using SystemVerilog and UVM and perform hands-on verification.
· Identify and write all types of coverage measures for stimulus and corner-cases.
· Debug tests with design engineers to deliver functionally correct design. blocks.
· Collaborate closely with all groups in active projects including Algorithm, FW, design and verification engineers.
· Close coverage measures to identify verification holes and to show progress towards tape-out.
· BSc. in Electronic Engineering MSc. an advantage
· At least 4 years’ experience as a verification engineer. Completing full development cycle an advantage.
· Knowledge in verification methodologies, tools (simulators and relative APIs, coverage tools, accelerators, formal, etc.), and techniques.
· Knowledge of Verilog and System Verilog.
· Experience in Python / Perl programming.
· Good knowledge of Unix environment and script languages.
· Methodological approach to building of verification environment and test plan.
· Methodological approach to the verification tasks planning and execution.
· Knowledge of UVM
Apply for this position
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